In recent years, a pixel size of the solid-state imaging device has been miniaturized. A layout of transistors may cause a variation of sensitivity among a plurality of photodiodes within a shared pixel.
To oppose this, there is a solid-state imaging device that inhibits sensitivity from varying among a plurality of photodiodes within a shared pixel by adopting a pixel transistor layout having symmetrical two transistor regions and sharing eight pixels (see Patent Document 1).
In the meantime, a high frame rate image capture is performed by a digital video camera in the related art in order to acquire a slow motion video, and capture an object to be imaged that moves quickly in sports broadcasting or the like.
In order to realize the high frame rate image capture, it is necessary to output immediately a signal from an amplification transistor included in each pixel to a vertical signal line, and to shorten the time for stabilizing the signal in a CMOS (Complementary Metal Oxide Semiconductor) image sensor mounted to a digital video camera, for example.
In order to achieve this, it is known that transconductance gm of the amplification transistor may be increased. In order to increase the transconductance gm, it is also known that a gate length L of the amplification transistor may be decreased or a gate width W thereof may be increased.
Patent Document 1: Japanese Patent Application Laid-open No. 2013-62789